1. Field of the Invention
This invention relates generally to the structure and fabrication process for manufacturing the junction field effect transistors (JFET). More particularly, this invention relates to a novel device structure and fabrication process for manufacturing normally on or normally off JFET transistors with low on-resistance for low voltage and high current density applications.
2. Description of the Prior Art
The semiconductor industry now faces a difficult challenge to satisfy the ever increased needs for providing transistors suitable for power management with voltage under three-volts. As the feature sizes of the integrated circuits (ICs) are becoming ever smaller and electronic devices are continuously being miniaturized, the voltages from AC or DC power sources for providing power to these devices are further dropped. Dropping the voltage from five volts to three volts results in a 25:9 reduction in power if the current density is maintained unchanged. At 1.8 volts, the power drops another 60%. However, the transient current loads can be very high. Under such operation conditions, the normal forward voltage drop for a p-n junction typically employed in a rectifier is about 0.9 volts. Most of the power will be consumed in the rectifying process. Power supply systems built with such types of p-n junctions would no longer be suitable for the low voltage applications. Even the Schottky barrier diodes with a forward voltage drop below 0.5 volts would not be a suitable solution to provide rectifiers or power switching devices for operation under the low voltage conditions.
The concept of junction filed effect transistors (JFETs) has been disclosed after the invention of the bipolar transistors. JFET transistor can be operated at very high frequency with high switching speed because the JFET transistors are operated with majority carriers. The JFET transistor are well known and employed commonly in a naturally on state when the gate bias is zero. Because of the naturally on state, the JFET transistor are not as widely used in the semiconductor industry as the MOSFET, i.e., the metal oxide semiconductor field effect transistors. In order to make the JFET transistors to operate in a naturally off state, the distance between the gates has to be reduced for the depletion regions from the gate to shut off the current conducting paths. Such naturally off JFET transistors are however not very useful in their conventional configurations due to the longer current channel thus limiting the current capacity with a high on-resistance. S. M. Sze in xe2x80x9cPhysics of Semiconductor Devicesxe2x80x9d disclosed one example of such configuration (John Wiley and Son, 1981 Second Edition, page 322). The normally off JFET transistors discussed by Sze are for high speed low power applications. The long current channel and high-on resistance limit the usefulness of JFET transistors particularly the high on-resistance prevents such transistors for application in modern electronic devices operated with extreme low voltages.
In U.S. Pat. No. 4,523,111 entitled xe2x80x9cNormally-Off Gate-Controlled Electric Circuit with Low On-Resistancexe2x80x9d, Baliga disclosed a JFET serially connected to an IGFET. The gate of IGFET is operated as the gate for the serially connected circuit. The gate of IGFET is applied to block the current to flow through a normally on JFET until the IGFET is turned on with a positively biased voltage above an IGFET threshold voltage. The on-resistance is the sum of the JFET resistance and the IGFET resistance. The on-resistance would not be adequate for extreme-low voltage applications required by modern electronic devices as discussed above. A similar invention is disclosed in U.S. Pat. No. 4,645,957 that is entitled xe2x80x9cNormally Off Semiconductor Device with Low On-Resistance and Circuit Analoguexe2x80x9d by Baliga. The JFET transistor is serially connected to a bipolar transistor to achieve the normally off state. Again, the on-resistance is the sum of the bipolar resistance and the JFET resistance and becomes too high for modern application to modern devices operated with extremely low voltages.
In U.S. Pat. No. 5,321,283 entitled xe2x80x9cHigh Frequency JFETxe2x80x9d Cogan et al. disclose a JFET for radio frequency (RF) operation at high frequency. The normally-on JFET transistors disclosed in this patent are operated with high voltage and not suitable to satisfy the requirements of modern portable electronic devices that require extremely low voltage and relatively high current capacity. Similarly, in U.S. Pat. No. 5,618,688 entitled xe2x80x9cMethod of Forming a Monolithic Semiconductor Integrated Circuit having an N-Channel JFETxe2x80x9d, Ruess et al disclose a normally on JFET transistor manufactured with BiCMOS processes. The JFET transistors disclosed in this patent are not suitable for low voltage and high current applications.
Therefore, a need still exits in the art of design and manufacture of transistor for low voltage power supply to provide a novel structural configuration and fabrication process that would resolve these difficulties. More specifically, it is preferably that the transistor for low voltage power supply has low on-resistance and high switching speed. It is further desirable to employ a simplified manufacture process to fabricate the power transistors such that highly reliable power transistors can be made available at a reasonably low production cost.
It is therefore an object of the present invention to provide new device structures and manufacture methods. The conventional JFET transistors, which are normally on with negatively biased off, are now provided with unconventional device structures such that the new JFET transistors are operated with low on-resistance and high current capacity that can be either normally on or normally off by arranging the distance between the gates. The unconventional JFET transistors of this invention provide special advantages for low-voltage low-resistance applications such that aforementioned limitations and difficulties as encountered in the prior art can be overcome.
Specifically, it is an object of the present invention to provide a new device structure and manufacture method to provide an unconventional JFET transistor with flexibly on-off adjustment. When the distance between the gates is sufficiently large, the JFET transistors are normally on with zero gate bias. As the distance between the gates is sufficiently small, the depletion regions from the gates fills the conduction paths between the gates thus the conduction paths are shut off and the JFET transistors are normally off with a zero gate bias and turned on with positive gate bias voltage. A positive or negative bias voltage applied to the gate causes the depletion regions surrounding the gate to shrink and open up the channel for current to pass through. Very low resistance current path is provided. Low voltage and high current density can be achieved by applying to the normally-off-positively-biased-on or normally-on-negatively-biased-off JFET transistors.
Another object of the present invention is to a new device structure and manufacture method for providing JFET transistors that can be flexibly configured by an unconventional device structure such that the JFET transistors can be either normally-off-positively-biased-on or normally-on-negatively-biased-off. The JFET transistors configured with unconventional structures are formed with low on-resistance, high current capacity and high switching speed. In a preferred embodiment, a horizontal JFET device is manufactured with standard CMOS processes with top and bottom gates controlling the drain to source current.
Another object of the present invention is to provide a new device structure and manufacture method for providing JFET transistors that can be flexibly configured by an unconventional device structure such that the JFET transistors can be either normally-off-positively-biased-on or normally-on-negatively-biased-off. In a preferred embodiment, a Schottky barrier is used as the top gate to achieve high switching speed. The barrier height is adjusted by controlling the implant dopant concentration or using different metal silicon or silicide/silicon systems.
Another object of the present invention is to provide a new device structure and manufacture method for JFET transistors that can be flexibly configured by an unconventional device structure such that the JFET transistors can be either normally-off-positively-biased-on or normally-on-negatively-biased-off. In a preferred embodiment, a deep implanted gate is formed in a multiple resistivity layers to provide gate control channel and to reduce the resistance of the drain/source ohmic contacts.
Another object of the present invention is to provide a new device structure and manufacture method for providing JFET transistors that can be flexibly configured by an unconventional device structure such that the JFET transistors can be either normally-off-positively-biased-on or normally-on-negatively-biased-off. In a preferred embodiment, a vertical gate pillar is used for a horizontal JFET transistor. The gate pillars can control the current flowed between deeper source and drain regions. Greater current density can be controlled without requiring greater silicon areas thus reducing the semiconductor real estate requirement for power transistor used for large current applications.
This invention is based on Applicant""s disclosures filed in the United States Patent and Trademark Office under the Disclosure Document Program. The disclosures filed are: 1) xe2x80x9cLow On Resistance Transistors and the Method of Makingxe2x80x9d #444899 filed on Sep. 24, 1998 and 2) xe2x80x9cNovel Structure of JFETs for Low Voltage Applicationsxe2x80x9d #444,874 filed on Sep. 17, 1998. This invention provides the advantages of low forward voltage drops between the source and drain. The voltage drops can be reduced to 0.1 volts or less and a current over 100 amperes for large size chips can also be achieved.
Briefly, in a preferred embodiment, the present invention discloses a junction field effect transistor (JFET) device supported on a substrate. The JFET device includes a gate surrounded by a depletion region. For a normally on JFET transistor, the depletion regions respond to a negative bias applied to the gate to turn off the current path. For a normally off JFET transistor, the depletion region responds to a positive bias applied to the gate to open a current path in the substrate wherein the current path in the substrate is shut off when the gate is zero biased. Special configurations are disclosed for normally on and normally off JFET transistors to shorten the current channels and to achieve low on-resistance, high current density and high switching speed.
The present invention also discloses a method for manufacturing a junction field effect transistor (JFET) device. The method includes the steps of a) forming a plurality of gates separated by a distance W wherein a depletion region surrounds each gate. And, b) adjusting a threshold voltage for the JFET transistor by gradually increasing a channel doping concentration near the depletion regions surrounding the gates for gradually decreasing the threshold voltage for the JFET transistor. In a preferred embodiment, the step of gradually increasing a channel doping concentration near the depletion regions surrounding the gates for gradually decreasing the threshold voltage is a step of making the JFET transistor with a threshold voltage greater than zero for providing a normally on JFET transistor. In a different preferred embodiment, the step of gradually increasing a channel doping concentration near the depletion regions surrounding the gates for gradually decreasing the threshold voltage is a step of making the JFET transistor with a threshold voltage equal or less than zero for providing a normally on JFET transistor. The distance, W, between gates can be determined by lithography, etch, and/or thermal process and can be reduced by RTA thermal process for threshold voltage adjustment prior to metalization.
These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment which is illustrated in the various drawing figures.